Add RISC V zvl flag for LLVM version 16 or greater. #7209
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added 5 commits
December 6, 2022 22:31
Add start of RISC V simd_op_check test.
steven-johnson
approved these changes
Dec 7, 2022
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Provides a way to configure a minimum vector length of the hardware via the target flags. Since Halide compiles to a specific vector length, passing this to the backend should provide better optimization.