ld4 is not emitted for int32 with vectorization factor 4

[stevesuzuki-arm]

If check(arm32 ? "vld4.32" : "ld4", 4, ld(in_f32, 4)); is added in simd_op_check_arm.cpp, it ends up with 8 scalar load instructions although one might expect a single ld4 instruction.
This seems to be an expected behavior as shown in staged_strided_loads.cpp "Strides up to the the vector size are worth densifying. After that, it's better to just gather."

What is the exact reason that this case is hindered? Is there any idea to make it happen?
The same applies to ld2 for int64 with vectorization factor 2

[abadams]

The thinking behind the comment in staged_strided_loads is that there's probably one underlying uop per vector accessed, plus some uops to do the transpose. This assumption may be specific to Apple silicon. Given that, it's probably better just to do one scalar load per vector accessed instead, even if it reads as more instructions.

This is a heuristic that I'm happy to tune. You can make it happen by changing StageStridedLoads.cpp:103 to be stride <= r->lanes instead of stride < r->lanes. Not sure what that means for things like small block transposes, because that's a case where you may have e.g. stride 16 and 16 lanes. Maybe it's better?

[stevesuzuki-arm]

Thanks! That makes sense.