[RISC-V] Enable crossgen for corelib

[clamp03]

This enables crossgen2 for corelib because

• We fixed many bugs on crossgen2. I think crossgen2 is enough for corelib.
• To prevent breaks on RISC-V, I want to add a checker in RISC-V build CI.

Actually, there are still some bugs like #97877, but I beleive that we can fix them soon.
+ To run with crossgened files on RISC-V, we need to disable EnableWriteXorExecute. (DOTNET_EnableWriteXorExecute=0)

Part of #84834
cc @dotnet/samsung

[clamp03]

@gbalykov IMO, the internal RISC-V CI will fail due to this PR. Please update the CI. Thank you!

[gbalykov]

@clamp03 thanks, let's see how it goes for a couple of days during the weekend and I'll check on Monday