Add initial support for Vector64 on Arm64 and Amd64#47618
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imhameed merged 13 commits intodotnet:masterfrom Feb 17, 2021
Merged
Add initial support for Vector64 on Arm64 and Amd64#47618imhameed merged 13 commits intodotnet:masterfrom
imhameed merged 13 commits intodotnet:masterfrom
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…trinsics.Vector64`1<byte>:get_Zero
…is enabled or type is 128
… a width-agnostic round-trip through memory instead of assuming 128-bit
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…ise vector initialization
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| #else | ||
| #define MONO_CLASS_IS_SIMD(cfg, klass) (((cfg)->opt & MONO_OPT_SIMD) && m_class_is_simd_type (klass)) | ||
| #define MONO_CLASS_IS_SIMD(cfg, klass) (((cfg)->opt & MONO_OPT_SIMD) && m_class_is_simd_type (klass) && (COMPILE_LLVM (cfg) || mono_type_size (m_class_get_byval_arg (klass), NULL) == 16)) | ||
| #endif |
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This means that non-arm64 only supports vector128 in non-llvm mode right ?
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Yeah. Maybe the enclosing preprocessor conditionals should be made more specific, and MONO_CLASS_IS_SIMD should expand to a constant "false" expression on everything other than x86, amd64, and arm64.
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Contributes to #42350
This change:
Conditionally marks Vector64 as a SIMD type. Vector64 is treated as a
SIMD type on amd64 and arm64 only when the LLVM backend is in use. Vector128
continues to be supported with both LLVM and mini on amd64, as before; on arm64,
it continues to only be supported with LLVM.
Checks vector widths for compatibility when bitcasting.
Slightly cleans up return value handling for SIMD value types--conversion
from an aggregate to an LLVM vector-typed value now happens in one location.
Removes a 128-bit SIMD assumption in the lowering code for OP_SETRET.
Renames
emit_vector128toemit_sri_vectorand makes it width-agnostic.Improves the generated IR for non-broadcasting Vector64/Vector128.Create; the
resulting code works entirely in registers and does not depend on temporary
stack storage for writing values into individual vector lanes.