RyuJIT: Remove redundant memory barrier for XAdd and XChg on arm

[EgorBo]

As far as I understand that memory barrier is not needed when we already emit LDADDAL and SWPAL with "acquire and release" semantics.

UPD: same for CASAL (emitted for Interlocked.CompareExchange)

For this reason I also replaced staddl with ldaddal for the case when we don't need the return value of Interlocked.Add.
Just like LLVM does: https://godbolt.org/z/a9GcT8

Here are the diff examples:

static int XAdd_ret(ref int x, int y) => Interlocked.Add(ref x, y);

G_M16300_IG01:
        A9BF7BFD          stp     fp, lr, [sp,#-16]!
        910003FD          mov     fp, sp
G_M16300_IG02:
        B8E10000          ldaddal w1, w0, [x0]
-       D5033BBF          dmb     ish
        0B010000          add     w0, w0, w1
G_M16300_IG03:
        A8C17BFD          ldp     fp, lr, [sp],#16
        D65F03C0          ret     lr

static void XChg_noret(ref int x, int y) => Interlocked.Exchange(ref x, y);

G_M24897_IG01: 
        A9BF7BFD          stp     fp, lr, [sp,#-16]!
        910003FD          mov     fp, sp
G_M24897_IG02: 
        B8E18000          swpal   w1, w0, [x0]
-       D5033BBF          dmb     ish
G_M24897_IG03:
        A8C17BFD          ldp     fp, lr, [sp],#16
        D65F03C0          ret     lr

/cc @dotnet/jit-contrib

[EgorBo]

NOTE: if targetReg is REG_NA (means we don't care about Interlocked.Add's return value) it uses WZR as a target register (it ignores writes and is always zero)

[VSadov]

As far as I understand that memory barrier is not needed when we already emit LDADDAL and SWPAL with "acquire and release"

The trailing dmb is needed after the LL/SC loop to make sure the whole thing acts as a full fence. Otherwise half-fenced stlxr could allow to observe speculative loads which happen while still inside the LL/SC loop, before the store is committed.

With InstructionSet_Atomics there is no loop and full-fence ordering can be explicitly requested, so no need for another fence.

[VSadov]

LGTM

[sandreenko]

LGTM