Add InstructionSet_VectorT for ARM64

[snickolls-arm]

Adds boilerplate code for an InstructionSet definition for the Vector<T> API surface, as we'll be needing an abstraction layer to redirect it to AdvSimd/SVE as appropriate for the target.

[snickolls-arm]

@dotnet/arm64-contrib

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[snickolls-arm]

The test failures look unrelated, this is ready for another review.

[stephentoub]

Code Review: PR #123992 - Add InstructionSet_VectorT for ARM64

Holistic Assessment

Motivation: Adding boilerplate for InstructionSet_VectorT to enable future Vector<T> redirection to SVE on ARM64.

Approach: Adds a new instruction set definition following the established patterns in the JIT infrastructure. The change correctly uses the instruction set generation system (InstructionSetDesc.txt) and manually updates related files to stay in sync.

Net Positive: ✅ This is foundational plumbing work needed for future SVE-based Vector<T> support. The approach is sound.

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Detailed Findings

⚠️ Design Consideration: DEBUG-only in Release VM Code

Files: src/coreclr/vm/codeman.cpp:1444-1452, src/coreclr/jit/compiler.cpp:5918-5927

The config value JitUseScalableVectorT is defined as CONFIG_DWORD_INFO (DEBUG-only) in clrconfigvalues.h, and the runtime code reads it only under #ifdef _DEBUG / #ifdef DEBUG.

However, the config definition uses EXTERNAL_ prefix which typically indicates a retail-accessible config. The mismatch is intentional here (experimental feature), but consider:

1. Documenting this is intentionally DEBUG-only for now
2. Or rename to INTERNAL_JitUseScalableVectorT to make the DEBUG-only intent clearer

✅ Correct Enum Ordering

The new InstructionSet_VectorT=12 is inserted between Vector128 and Dczva, which renumbers subsequent enums. This is correctly synchronized across:

• corinfoinstructionset.h
• CorInfoInstructionSet.cs
• hwintrinsic.cpp array entries

✅ JIT-EE GUID Updated

The JITEEVersionIdentifier GUID is correctly updated in jiteeversionguid.h, which is required when instruction set enums change.

✅ Implication Chain Correct

The InstructionSetDesc.txt correctly declares:

• vectorinstructionset,ARM64,VectorT - marks it as a vector ISA
• implication,ARM64,VectorT,Sve - VectorT implies SVE support

The generated code in CorInfoInstructionSet.cs correctly propagates these implications in both forward and reverse directions.

✅ ReadyToRun Handling

ReadyToRunInstructionSetHelper.cs returns null for ARM64_VectorT, which is correct - this is a JIT-only concept not persisted in R2R images.

💡 Suggestion: Consider Ordering in InstructionSetDesc.txt

In the PR diff, VectorT is added after Vector128 but the implication line is added after Vector128 implication. This is fine, but for better grouping, consider placing VectorT-related entries near VectorT128 since they are conceptually related (both are Vector<T> implementations).

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Test Coverage

This PR adds infrastructure only with no behavioral changes in non-DEBUG builds. The DEBUG-only code paths are gated behind a config switch that defaults to off. Future PRs implementing actual Vector<T> SVE support should include tests.

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Summary

Verdict: ✅ Approve

This is clean infrastructure work that follows established patterns in the codebase. The changes are correctly synchronized across all the instruction set definition files. The DEBUG-only gating is appropriate for experimental features.

Minor suggestion: Consider using INTERNAL_ prefix instead of EXTERNAL_ for the config value to make the DEBUG-only nature more explicit in the naming.

[snickolls-arm]

@tannergooding I think these test failures are unrelated, but I've disabled your auto-merge responding to Stephen's comment.

[tannergooding]

/ba-g unrelated http timeout