Do tgtPrefUse for ARM64

[kunalspathak]

As pointed by @tannergooding in #36156 (comment) , add tgtPrefUse and tgtPrefUse2 for ARM64 hardware intrinsic operations.

category:cq
theme:register-allocator
skill-level:expert
cost:medium

[tannergooding]

@CarolEidt, when I was looking at the existing LSRA logic for ARM64, it didn't look like we were using tgtPrefUse anywhere but the HWIntrinsics logic (and we aren't using tgtPrefUse2 anywhere). Do you know why that is?

My initial guess is because most ARM instructions aren't RMW...

[CarolEidt]

Yes, it's because most ARM instructions aren't RMW, though I suspect there are places we should be using it for things that turn into a simple move.

[echesakov]

@kunalspathak This is already supported for RMW HW intrinsics (see my comment #36156 (comment)) We can add setting tgtPrefUse to op1Reg or op2Reg for more intrinsics and I suggested to use declarative approach (i.e. specifying this in hwintrinsiclistarm64.h)

[tannergooding]

(Mostly copying my comment from #36156 (comment))

I'd want to wait and see how many instructions actually fit this category. I'd imagine on ARM it is largely restricted to RMW (in which case the RMW flag covers it) and specially handled moves where we can make it zero cost for specific types (float/double).
If it is ultimately just going to be the moves and it only applies to float/double (due to sharing the SIMD register), I don't think adding logic for the declarative model will be worthwhile.

For example, on x86, we really only had to special case FMA (because it is a 3 op, commutative RMW instruction) and the ToScalar methods for float/double.

[AndyAyersMS]

Marking this as future since benefit seems unclear.

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