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math_lib

math_lib is a collection of hardware mathematical function implementations in Verilog, including logarithm, trigonometric functions, and floating-point format conversions.

Directory Structure

.
├── rtl/                    # Verilog RTL source files
├── sim/                    # Simulation
│   ├── Makefile
│   ├── modules.mk
│   └── tb/                 # Testbenches
└── README.md

Modules

Module	Description	Parameters
log2	Integer logarithm base 2 (equivalent to $clog2). Returns the number of bits needed to represent the input value. Combinational logic with 0 latency.	DATA_WIDTH
int_sin	CORDIC algorithm implementation for Sine and Cosine functions. Supports pipelined and non-pipelined modes.	DATA_WIDTH, ANGLE_WIDTH, PIPELINE
int_to_float	32-bit Integer to IEEE 754 Single-Precision Floating-Point Converter. Optional pipelined mode.	PIPELINE
float_to_int	IEEE 754 Single-Precision Floating-Point to 32-bit Integer Converter. Rounding mode: round to nearest.	PIPELINE
float_to_double	Single-Precision to Double-Precision Floating-Point Converter.	PIPELINE
double_to_float	Double-Precision to Single-Precision Floating-Point Converter.	PIPELINE
long_to_double	64-bit Long Integer to IEEE 754 Double-Precision Floating-Point Converter.	PIPELINE
double_to_long	IEEE 754 Double-Precision Floating-Point to 64-bit Long Integer Converter.	PIPELINE

Run Simulation

1. Run All Modules

Execute the following command in the sim directory to verify all modules:

cd sim
make

2. Run Specific Module

To run a specific module testbench:

cd sim/tb/log2_tb
make

Each testbench generates a waveform.vcd file (viewable in GTKWave).

3. Clean Build

make clean

Environment

Please ensure the following tools are installed:

• Verilator
• GTKWave (Optional, for waveform viewing)
• Make
• GCC/G++

License

MIT License

Copyright (c) 2025 WanderingKitsune

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math_lib

math_lib 是一个用 Verilog 编写的硬件数学函数库，包括对数函数、三角函数和浮点数格式转换等功能。

目录结构

.
├── rtl/                    # Verilog RTL 源代码
├── sim/                    # 仿真
│   ├── Makefile
│   ├── modules.mk
│   └── tb/                 # 测试平台
└── README.md

模块说明

模块	描述	参数
log2	整数对数基底 2（等价于 $clog2）。返回表示输入值所需的位数。组合逻辑，零延迟。	DATA_WIDTH
int_sin	CORDIC 算法实现的正弦和余弦函数。支持流水线和非流水线模式。	DATA_WIDTH, ANGLE_WIDTH, PIPELINE
int_to_float	32 位整数转 IEEE 754 单精度浮点数转换器。可选流水线模式。	PIPELINE
float_to_int	IEEE 754 单精度浮点数转 32 位整数转换器。舍入模式：四舍五入。	PIPELINE
float_to_double	单精度转双精度浮点数转换器。	PIPELINE
double_to_float	双精度转单精度浮点数转换器。	PIPELINE
long_to_double	64 位长整数转 IEEE 754 双精度浮点数转换器。	PIPELINE
double_to_long	IEEE 754 双精度浮点数转 64 位长整数转换器。	PIPELINE

运行仿真

1. 运行全部模块

在 sim 目录下执行以下命令验证所有模块：

cd sim
make

2. 运行指定模块

运行特定模块的测试平台：

cd sim/tb/log2_tb
make

每个测试平台都会生成 waveform.vcd 文件（可用 GTKWave 查看）。

3. 清理构建

make clean

环境要求

请确保已安装以下工具：

• Verilator
• GTKWave（可选，用于查看波形）
• Make
• GCC/G++

版权说明

MIT License

Copyright (c) 2025 WanderingKitsune